1. Field of the Invention
The present invention relates to a carrier phase synchronizing circuit, in particular to, a carrier phase synchronizing circuit for use with a demodulator for receiving a modulated wave that is used for a communication system such as a non-stationary satellite of which a carrier frequency largely fluctuates.
2. Description of the Related Art
In a satellite communication system of which a burst signal of for example a voice signal should be transmitted on real time basis, the phase of the burst signal that is sent from an earth station, a satellite, or a terminal unit should be synchronized at high speed. However, the carrier frequency has an offset due to a Doppler shift, a drift of the local oscillator of the earth station or the satellite. The offset of the carrier frequency adversely affects the establishment of the synchronization of the carrier frequency. Conventionally, the synchronization of the carrier frequency against the offset is established by the following method.
FIG. 3 is a block diagram showing an example of a carrier phase synchronizing circuit using a conventional primary phase synchronizing loop (or phase lock loop PLL). The phase of a quasi-coherently detected output signal and the phase of an output signal of a voltage controlling oscillator (VCO) 20 that oscillates in accordance with a control voltage are compared by a phase comparator 17. An output signal of the phase comparator 17 is supplied to a phase detector 18. The phase detector 18 outputs phase error information. The phase error information is smoothed (filtered) by a low pass filter of a loop filter 19 and a output of the loop filter 19 supplied as the control voltage to the voltage controlling oscillator 20.
In the case that a receive signal contains an angular frequency offset .DELTA..omega. (=2.pi..DELTA.f) of a carrier frequency, if the phase detector 18 with sine wave characteristics is used, a non-linear differential equation of first order that represents the response of a phase error .theta..sub.e (t) following expression is given by the following formula. EQU d.theta..sub.e (t)/dT=.DELTA..omega.-K sin .theta..sub.e (t)(1)
where K is a loop gain. To allow the phase of the carrier frequency to be synchronized and the carrier frequency to be stable, the following relation should be satisfied. EQU d.theta..sub.e (t)/dT=0.
With the formula (1), the following relation should be satisfied. EQU .vertline..DELTA..omega./K.vertline.=.vertline.2.pi..DELTA.f/K.vertline..lt oreq.1 (2)
The formula (2) represents that when the frequency offset .DELTA.f exceeds K/2.pi., the phase is not locked. When the loop gain K becomes large, the range of the carrier frequency that can be captured becomes wide. However, when the loop gain K becomes large, the phase jitter of the reproduced carrier can be decreased while the condition of a low C/N is satisfied. Thus, the range of the carrier frequency that can be initially captured with the primary PLL has a limit. The carrier phase synchronizing circuit using the primary PLL can be simply structured. In addition, the circuit does not need adjustments. Therefore, the demodulating unit can be accomplished at low cost. However, when the initial frequency error is out of the frequency capturing range of the PLL, the synchronized phase of the carrier frequency cannot be captured and synchronized.
FIG. 4 is a block diagram showing an example of a carrier phase synchronizing circuit that allows a frequency to be captured with a large frequency error as disclosed in Japanese Patent Laid-Open Publication No. 5-41717. In FIG. 4, a frequency error detecting circuit 27 detects a frequency error. When the frequency error is larger than a predetermined value, the carrier frequency signal is captured with an AFC loop composed of a frequency error detecting circuit 27, an automatic frequency controlling (AFC) loop filter 28, a sample hold circuit 29, a numeric controlling oscillator 30, a multiplying device 21, a low-pass filter 22, a multiplying device 23, and a phase detector 24. On the other hand, when the frequency error becomes smaller than a predetermined value, the sample hold circuit 29 holds an output control signal of the AFC 28 with a control signal of the frequency error detecting circuit 27. Then a PLL composed of a loop filter 25, a numeric controlling oscillator 26, the multiplying device 23, and the phase detector 24 performs the PLL operation instead of the AFC loop operation. Thus, even if the frequency error becomes large, the carrier frequency can be captured at high speed and stability.
In the conventional carrier phase synchronizing circuit using the PLL, the AFC loop or the PLL is selected depending on the magnitude of the frequency error. Thus, even if the frequency error is large, the carrier frequency can be captured at high speed. In addition, the phase of the carrier frequency can be stably synchronized. However, in the case that the carrier frequency of a receive signal fluctuates time by time as with a non-stationary satellite in particular a low orbit satellite communication, since the frequency error detected by the PLL fluctuates time by time, it is not effective to switch the loops depending on the magnitude of the frequency error. Thus, it is difficult to capture the carrier frequency at high speed and to stably synchronize the phase of the carrier frequency.